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Known Issues VisualApplets Release 3.1.1#

Windows 10 Fall Creators update (version 1709) on a PC with a Vivado 2017.2 or Vivado 2017.3 Installation

If you install the Windows 10 Fall Creators update (version 1709) on a PC that has Xilinx Vivado version 2017.2 or 2017.3 installed, Xilinx Vivado may not properly work afterwards. Thus, you may not be able to build the designs you created with VisualApplets. |

Follow the work-around provided by Xilinx Support to make your Xilinx Vivado 2017.2 or 2017.3 installation work again. (See https://www.xilinx.com/support/answers/69908.html).

Windows 10 x64 (version 1803) Cumulative Update from 2017-07-10 (KB4338819) on a PC with a ISE 14.7 or Vivado installation older than 2017.4

If you install the above Windows 10 update the build flow may not work properly afterwards using Xilinx tools older than Vivado 2017.4. Thus, you may not be able to build the designs you created with VisualApplets.

For Vivado versions older than Vivado 2017.4 error messages may show up in the log output of the Xilinx tool chain telling that some black box instances have undefined content. For ISE® even no Xilinx tool version can be determined and the FPGA Type Check fails. Though the 32 bit tool chain of ISE® works (change the Build Settings: For Xilinx settings batch file use settings32.bat instead of settings64.bat).

Follow the work-around provided by Xilinx Support to make the ISE installation work again (See https://www.xilinx.com/support/answers/62380.html, section ISE 14.7 64bit - Turning off SmartHeap). The same work-around can be used for Vivado where you need to perform the file substitution actions in the folder \<VivadoInstallDir>/ids_lite/ISE/lib/nt64. |

  1. User-independent installation of VisualApplets in directory programs (Windows) results in access problems.

  2. When you build an applet using the Xilinx Vivado Tools, you may get critical warnings (in build step LinkDesign). The warnings are due to an issue within the Xilinx tool chain. The issue is known to Xilinx and fixing is in progress. However, as this issue is NOT CRITICAL for designs created in VisualApplets, the warnings can be ignored. Example:

    CRITICAL WARNING: [Shape Builder 18-137] Cannot obey LUTNM/HLUTNM constraint
for instances …/PART1174 and …/PART1175. Illegal to place instance
…/PART1174 on site SLICE_X2Y0. The location site type does not match the
instance type. Instance …/PART1174 belongs to a shape with reference instance
…/PART1175. Shape elements have relative placement respect to each other.
The invalid location might results from a constraint on any of the instance
in the shape..

  3. File names: For naming *.va files, only fonts based on ASCII characters can be used; this means that, e.g., Asian, Cyrillic, Greek, or Arabic fonts are not supported for file names.

  4. Bandwidth dialog in designs for microEnable 5 marathon and LightBridge frame grabbers: The values displayed for memory-based operators are not reliable. The actual data throughput of the memory operators may differ because the bandwidth analysis doesn’t factor in the shared RAM concept implemented in marathon and LightBridge frame grabbers. If an operator shares the RAM with other operators, this is not detected by the bandwidth analysis and therefore is not reflected in the displayed values.

  5. Only the first started instance of VisualApplets is able to save its configuration. All VisualApplets instances that have been started later have only a temporary configuration which will be discarded when the instance is closed. This concerns, e.g., build settings, library settings, system settings, general VisualApplets settings.

  6. Hierarchical Boxes: If you are using hierarchical boxes, in some specific situations, the Design Rule Check may come up with the following error message: "The input XYZ of the operator ABC (hierarchical box) must be connected to an O-type operator, e.g., NOP." The reason is that some M-type operators placed within a hierarchical box cannot be connected to the input port of the hierarchical box directly. This is only true for some specific M-type operators. You can solve this problem (within the hierarchical box) by placing an NOP operator between the input port of the hierarchical box and the input port of the M-type operator.

  7. SDK for CXP: Accesses to the SISO_GenICam library are not generated automatically, but have to be programmed by the user.

  8. Applets for microEnable 5 platforms have to be loaded onto the frame grabber via Firmware flasher tool (microDiagnostics) in order to change the applet.

  9. Bandwidth analysis does not show exact values and is only an estimation. Use this feature very carefully and run additional tests on the target hardware. Bandwidth calculation in case of kernel operations does not consider kernel dimensions.

  10. Operators of the color library should be used carefully: Some color conversions don't work as a user would assume:

    • HSI2RGB converts HSL -> RGB ,
    • RGB2YUV converts RGB->YCbCr,
    • XYZ2LAB uses constants according to the following definitions: www.easyrgb.com

  11. Operator FIRKernelNxM may cause processing errors in case the parameter EdgeHandling is set to constant, the number of columns > 2*parallelism, the number of kernel columns is an even number, and parallelism > 1. The error can be monitored at the left border of an image, where wrong pixel data is used at the kernel positions inside the frame.

  12. After a simulation error has occurred, the simulation conditions need to be reset.

  13. Trigger operators may cause spikes at the trigger output line during initialization phase when loading the applet onto the frame grabber.

  14. Important note concerning operating systems Microsoft Windows 8 and 7 32bit/64bit, Microsoft Windows Vista 32bit/64bit and Microsoft Windows XP 64bit: It is necessary and recommended to define the user folder as destination folder. Alternatively any other folder with full access rights can be used.

  15. The DMA resource indexes have to start with zero and have to be consecutively numbered. This will be checked by the DRC.

  16. The operator ImageBufferMultiRoiDyn may cause timing errors in case of very small input images.

  17. The operator ImageSequence may cause build errors (timing errors). (2422)

  18. BAYER5x5Linear: In some cases, the resource estimation in VisualApplets for this operator (in dialog FPGA Resource Usage) might differ from the estimation displayed by the XilinX tools after Place & Route. (6426)

  19. In some cases, changing the platform for a design may lead to the error message "Invalid parameter value: RamDataWidth is not accepted" during the design rules check. This may happen for modules which are using the resource RAM when the new target platform has a different memory layout than the previous platform. To resolve this, save and reload the design. (8708)

  20. Operator ModuloCount: Parameter Devisor can be theoretically set to a value up to 64 bit, but any parametrization with a value higher than 32 bit causes VisualApplets to crash during simulation. (8901)

  21. DynamicROI: Under specific conditions, operator DynamicROI outputs a wrong line length (the output line length is wrongly extended by one parallel word). This fault occurs only if all of the following three conditions are met:

    • Parallelism is not power of two,
    • Xoffset is divisible by parallelism, and
    • Xlength is divisible by parallelism.

    If one of these conditions is not met, operator DynamicROI works correctly. This fault occurs in the FPGA implementation. The simulation simulates the correct operator behavior. (7722)

  22. The SampleDn operator produces a corrupted image when used with a sampling factor that is dividable by 2 and a parallelism higher than 1.

  23. Custom operators, memory access: With specific access patters, memory access out of custom operators resulted in data corruption in VisualApplets versions 3.0.6, 3.1, 3.1.1, and 3.1.2. This issue has been fixed in VisualApplets version 3.2.