Known Issues VisualApplets Release 3.5.0
Info
If you install the Windows 10 Fall Creators update (version 1709) on a computer that has Xilinx Vivado version 2017.2 or 2017.3 installed, Xilinx Vivado may not work properly. Thus, you may not be able to build the designs you created with VisualApplets.
Follow the workaround provided by Xilinx Support to make your Xilinx Vivado 2017.2 or 2017.3 installation work again.
Info
If you install the above Windows 10 update, the build flow may not work properly using Xilinx tools older than Vivado 2017.4. Thus, you may not be able to build the designs you created with VisualApplets.
For Vivado versions older than Vivado 2017.4, error messages may show up in the log output of the Xilinx tool chain telling that some black box instances have undefined content. For ISE, no Xilinx tool version can be determined and the FPGA type check fails.
Follow the workaround provided by Xilinx Support to make the ISE installation work again (section "ISE 14.7 64-bit - Turning off SmartHeap"). The same workaround can be used for Vivado where you need to perform the file substitution actions in the <VivadoInstallDir>/ids_lite/ISE/lib/nt64 directory.
General
| Summary: | For mE5 Platforms and imaFlex Platforms the Resource Estimation May Be Too Low |
| Description: | For mE5- and imaFlex platforms, the resource estimation for some operators (i.e. Blob and Histogram) may underestimate the number of used block RAMs. Depending on the module configuration, the real usage of block RAM ressources can be more than 50 % higher. |
| Workaround: | No workaround is available. |
| Ticket ID: | 297790 |
| Summary: | Copying Content Using the Clipboard Doesn’t Work |
| Description: | It's not possible to copy design content from designs opened in this VisualApplets version into designs opened in VisualApplets versions 3.3.2 or earlier using the clipboard (copy&paste). However, copying from any VisualApplet version to this version works. |
| Workaround: | Save your design in the legacy *.va file format, open it in an older version of VisualApplets and copy the content from there. |
| Ticket ID: | – |
| Summary: | RGB Images Loaded into the Simulation Probe Viewer Might Be Saved as Mono Image (8 Bit) |
| Description: | In the Simulation Probe Viewer, RGB images that contain the same values across the color channels are saved as mono image (i.e. 8-bit image), not as 24-bit image. |
| Workaround: | If you want to preserve the channels, save your image in the BMP file format. |
| Ticket ID: | 266977 |
| Summary: | Xilinx ISE Build Tool Chain Doesn't Support Windows 11 |
| Description: | The Xilinx ISE build tool chain doesn't support Windows 11. Therefore, building VisualApplets designs doesn't work with Xilinx ISE. |
| Workaround: | If you want to build applets for platforms that need to be built with Xilinx ISE, install VisualApplets under Windows 10. If your target platform is supported by Vivado, build the applets with Xilinx Vivado (Vivado supports Windows 11). See in the system requirements section which platforms are supported by Vivado. |
| Ticket ID: | 236990 |
| Summary: | Applets for mE5-CL Platforms Can't Be Built with some Xilinx Vivado Versions |
| Description: | Applets for mE5-CL platforms can't be built with Vivado versions between 2020.2 and 2021.1. |
| Workaround: | This problem has been fixed with Xilinx Vivado version 2021.2. Thus, to avoid this problem, use Vivado version 2021.2 or higher. |
| Ticket ID: | 217879 |
| Summary: | When Converting a Design to a Different Hardware Platform, the Hardware-Dependent Operator Library Might Not Be Available |
| Description: | When converting a VisualApplets design to a different hardware platform, under certain circumstances the hardware-dependent operator library for the target platform might not be available. |
| Workaround: | To resolve this, restart VisualApplets. |
| Ticket ID: | – |
| Summary: | Xilinx Vivado Warning When Building an Applet |
| Description: | When you build an applet using the Xilinx Vivado tools, you may get critical warnings (during the LinkDesign build step). The warnings are due to an issue within the Xilinx tool chain. The issue is known to Xilinx and fixing is in progress. Example:
CRITICAL WARNING: [Shape Builder 18-137] Cannot obey LUTNM/HLUTNM constraint for instances …/PART1174 and …/PART1175. Illegal to place instance …/PART1174 on site SLICE_X2Y0. The location site type does not match the instance type. Instance …/PART1174 belongs to a shape with reference instance …/PART1175. Shape elements have relative placement respect to each other. The invalid location might result from a constraint on any of the instance in the shape..
|
| Workaround: | Ignore the warnings. This issue is not critical for designs created in VisualApplets. |
| Ticket ID: | – |
| Summary: | Only ASCII Characters Are Supported for *.va File Names |
| Description: | For naming *.va files, only fonts based on ASCII characters can be used; this means that, e.g., Asian, Cyrillic, Greek, or Arabic fonts are not supported for file names. |
| Workaround: | No workaround is available. |
| Ticket ID: | – |
| Summary: | Configuration Is Only Saved For First Instance of VisualApplets |
| Description: | Only the first started instance of VisualApplets is able to save its configuration. All VisualApplets instances that are started later have only a temporary configuration which will be discarded when the instance is closed. This concerns, e.g., build settings, library settings, system settings, general VisualApplets settings. |
| Workaround: | No workaround is available. |
| Ticket ID: | – |
| Summary: | Design Rules Check Error When M-Type Operators in a Hierarchical Box Are Connected Directly to the Input Port |
| Description: | If you are using hierarchical boxes, in some specific situations, the Design Rules Check may come up with the following error message: "The input XYZ of the operator ABC (hierarchical box) must be connected to an O-type operator, e.g., NOP." The reason is that some M-type operators placed within a hierarchical box cannot be connected to the input port of the hierarchical box directly. This is only true for some specific M-type operators. |
| Workaround: | You can solve this problem (within the hierarchical box) by placing a NOP operator between the input port of the hierarchical box and the input port of the M-type operator. |
| Ticket ID: | – |
| Summary: | Design Rules Check Error When Using the Line-by-Line 1D Simulation Mode |
| Description: | For some designs which passed the Design Rules Check in former versions of VisualApplets, link errors concerning the maximum image height may be reported. In particular, this may happen when 1D processing is involved and the new line-by-line simulation mode is activated (default). The reason is that in the line-by-line-mode some operators propagate the max. image height of input links in a different way to the output links than before. |
| Workaround: | You can solve this problem by changing to the legacy simulation mode or by adding SetDimension modules for adjusting the maximum image height values. |
| Ticket ID: | – |
| Summary: | Increased Operating Time When Using the Line-by-Line 1D Simulation Mode |
| Description: | For some designs the operating time for simulation may be much higher than in former versions of VisualApplets. In particular, this may happen when 1D processing is involved, the new line-by-line simulation mode is activated (default), and the design contains many simulation probes. |
| Workaround: | You can solve this problem by changing to the legacy simulation mode or by reducing the number of simulation probes. |
| Ticket ID: | – |
| Summary: | SDK for CXP: Accesses to the SISO_GenICam Library Have to Be Programmed by the User |
| Description: | SDK for CXP: Accesses to the SISO_GenICam library are not generated automatically, but have to be programmed by the user. |
| Workaround: | No workaround is available. |
| Ticket ID: | – |
| Summary: | Increasing the FPGA Design Clock Frequency May Lead to Slow Builds |
| Description: | Increasing the FPGA design clock frequency may have the result that the build flow takes very long or even fails because timing constraints cannot be met. This strongly depends on the content of the VisualApplets design. |
| Workaround: | No workaround is available. |
| Ticket ID: | 8513 |
| Summary: | Large Images Are Not Displayed in Simulation Probes |
| Description: | When simulation probes contain very large images, VisualApplets may fail to display these images correctly due to memory limitations. In that case, a gray image (i.e. all pixels have the value 205 (0xCD)) is shown. |
| Workaround: | Use smaller images for simulation. |
| Ticket ID: | 6822 |
| Summary: | Simulation Only Supports Images Smaller than 2 GB |
| Description: | During simulation the internal buffer size for any image is limited to 2 GB. For simulations with images larger than 2 GB, the simulation is stopped with an error message. |
| Workaround: | Use images smaller than 2 GB for simulation. |
| Ticket ID: | 240989 |
Blob_Analysis_1D Operator
| Summary: | The Blob_Analysis_1D Operator Sets the object size exceeds maximum Flag Not as Expected |
| Description: | If an object is truncated due to exceeding the maximum size defined by the max_object_height_bits parameter, the corresponding object size exceeds maximum flag is set in the truncated object and not in the proceeding object. |
| Workaround: | No workaround is available. |
| Ticket ID: | 9685 |
| Summary: | The Blob_Analysis_1D Operator Does Not Set the label overflow Flag |
| Description: | The label overflow flag indicating that all labels are in use and the current object cannot be tagged, is never set. |
| Workaround: | No workaround is available. |
| Ticket ID: | 9691 |
| Summary: | The Blob_Analysis_1D Operator Allows 20 Labels Less Than Defined per Line |
| Description: | The amount of available labels as defined by the Label_bits parameter is reduced by 20 labels. For example, if Label_bits is set to 5, only 12 (2^5 - 20) labels are available, and not 32 as expected (2^5). |
| Workaround: | No workaround is available. |
| Ticket ID: | 9688 |
| Summary: | The Simulation of The Blob_Analysis_1D Operator is Not Equal to Hardware Behavior |
| Description: | The order of the object feature output might differ in hardware and software. This is so, because the hardware output depends on the timing of the data which cannot be simulated in VisualApplets. Additionally, the FlushI input is asynchronous to the image data input, so completing output frames may not be simulated in a realistic way. |
| Workaround: | No workaround is available. |
| Ticket ID: | 7709 |
Library Color
| Summary: | Some Color Conversions Don't Work As Expected |
| Description: | Operators of the Color library should be used carefully: Some color conversions don't work as a user would assume:
- HSI2RGB converts HSL -> RGB
- RGB2YUV converts RGB->YCbCr
- XYZ2LAB uses constants according to the following definitions: www.easyrgb.com
|
| Workaround: | No workaround is available. |
| Ticket ID: | – |
| Summary: | Limitations for Negative Transformations Coefficients |
| Description: | The ColorTransform operator supports negative transformation coefficients only in the case where the input format is signed or the coefficients are static. |
| Workaround: | No workaround is available. |
| Ticket ID: | 251344 |
BAYER5x5Linear Operator
| Summary: | The Resource Estimation in VisualApplets for BAYER5x5Linear Differs From the Estimation in Xilinx |
| Description: | BAYER5x5Linear: In some cases, the resource estimation in VisualApplets for this operator (in FPGA Resource Usage dialog) might differ from the estimation displayed by the Xilinx tools after Place & Route. |
| Workaround: | No workaround is available. |
| Ticket ID: | 6426 |
Library Compression
JPEG_Encoder Operator
| Summary: | The Output Transfer Of the JPEG_Encoder Operator Starts Earlier Than the Actual Image Data Transfer |
| Description: | Operator: To optimize its image throughput rate (band width), the operator outputs the header as soon as header generation is activated - even before image data arrive at the operator's input. This way, the transfer of the header data doesn't interrupt the transfer of image data, as the header is transferred in advance. The drawback of this practice is that the operator's output transfer starts earlier than the actual image data transfer. This may cause irritations under specific circumstances:
If you are using the SourceSelector operator directly after JPEG_Encoder: The SourceSelector operator registers a partly processed frame as soon as it gets the header data. Therefore, if SourceSelector is switched to getting image data from JPEG_Encoder, SourceSelector cannot be switched to any another source as it always detects an unfinished frame. In addition, when header generation is enabled and SourceSelector switches from another source to the JPEG_Encoder channel, the first image is lost. |
| Workaround: | If working on eVA devices, make sure the output is capable to accept data transfer before the sensor transfer is started. |
| Ticket ID: | – |
Library Debugging
ImageFlowControl Operator
| Summary: | Damaged Frame After an Overflow Situation |
| Description: | Using the ImageFlowControl operator in dummy frame generation mode may result in a damaged frame as output. This happens after an overflow situation, when a series of dummy frames is emitted for compensating lost frames. |
| Workaround: | No workaround is available. |
| Ticket ID: | 248227 |
Library Filter
DILATE Operator
| Summary: | In the Hardware Implementation of the DILATE Operator, the Structuring Element Is Rotated |
| Description: | The hardware implementation of the DILATE operator differs from the simulation and the documentation. In the hardware inplementation, the structuring element is rotated. |
| Workaround: | No workaround is available. |
| Ticket ID: | 267460 |
FIRKernelNxM Operator
| Summary: | FIRKernelNxM Operator May Cause Processing Errors |
| Description: | The FIRKernelNxM operator may cause processing errors in case the EdgeHandling parameter is set to constant, the number of columns > 2*parallelism, the number of kernel columns is an even number, and parallelism > 1. The error can be monitored at the left border of an image, where wrong pixel data is used at the kernel positions inside the frame. |
| Workaround: | No workaround is available. |
| Ticket ID: | 2939 |
Trigger Operators
| Summary: | Trigger Operators May Cause Spikes at the Trigger Output Line |
| Description: | Trigger operators may cause spikes at the trigger output line during initialization phase when loading the applet onto the frame grabber. |
| Workaround: | No workaround is available. |
| Ticket ID: | – |
Library Memory
ImageBufferMultiRoiDyn Operator
| Summary: | Timing Errors with Small Images |
| Description: | The ImageBufferMultiRoiDyn operator may cause timing errors in case of very small input images. |
| Workaround: | No workaround is available. |
| Ticket ID: | – |
| Summary: | The ImageBufferMultiRoiDyn Operator Doesn't Work Correctly for ROI Width Values Equal to Parallelism |
| Description: | If the value of ROI Width is equal to the value of Parllelism, the ROI isn't read out as expexted. Instead, the first pixel/line is repeated ROI Height times. |
| Workaround: | No workaround is available. |
| Ticket ID: | 307592 |
ImageSequence Operator
| Summary: | Build Errors Caused by the ImageSequence Operator |
| Description: | The ImageSequence operator may cause build errors (timing errors). |
| Workaround: | No workaround is available. |
| Ticket ID: | 2422 |