Changes and Fixed Issues in VisualApplets 3.2.1#

Tcl (Expert Feature)#

Scripting commands CopySelected and CutSelected did not copy any content to the clipboard. This has been fixed. (9595)
Text can be copied from the Tcl window now under all circumstances. In earlier versions, copying didn't work when an operator or link was selected. This has been fixed. (9455)

In earlier versions, a memory leak occurred when operator RamLUT was simulated. This memory leak during simulation has been fixed. (9635)

Certain image content caused a crash during simulation. This has been fixed. (9642)

Operator RemovePixel could cause a crash of VisualApplets during simulation. This has been fixed. (6707)

Operator ImageTimingGenerator could cause a crash of VisualApplets during simulation in 0D or 1D mode. This has been fixed. (9633)

In designs utilizing PixelToSignal modules during simulation, in some cases an early abort of processing could occur when the simulation of data flow synchronization was activated (default). This has been fixed. (9622)

In designs utilizing PixelToImage modules during simulation, in some cases an early abort of processing could occur when the simulation of data flow synchronization was activated (default). This has been fixed. (9622)
PixelToImage now uses a simple simulation model emitting a zero pixel for each incoming pixel at port Sample.

Operator ImageFifo now detects when a given parametrization would exceed available FPGA memory resources. The operator now triggers an according error message. (8875)

The JPEG_Encoder operator can now be used also with non-stoppable sources. In this context, a new parameter InfiniteSource and an overflow management has been implemented. To use the operator with non-stoppable sources, you need to set parameter InfiniteSource to Enabled.

Under certain conditions, converting a design to a different platform failed, resulting in a corrupted design file. This has been fixed. (9626)

The CameraLink interface on VCL/VCLx platforms was missing clock management placement constraints. In most designs, Vivado placed the related clock managers still in correct positions due to the correspondent IO pin locations. However, under unknown circumstances it could happen that Vivado created an illegal placement which lead to an error in the Place & Route build step. The placement of the CameraLink clock managers is now fixed and thus, this issue can never occur again. (9648)

For writing and reading of 64 bit integer field parameters, no appropriate code was generated. This has been fixed. (9653)

The visibility of the current FPGA clock setting (for mE5 designs) has been improved. Furthermore, a warning message occurs when the clock frequency is set to a very high value, as increasing the clock frequency may result in a build flow fail because the timing constraints can't be met. Whether the build flow with high clock settings succeeds or not strongly depends on the content of the VisualApplets design. (8513)\

You can save the content of the panes "DRC Log" and "Build Log" to *.txt files. This was not working correctly, but has been fixed now. (9404)

When the reference parameter of an HBox module is changed: As soon as you click the Apply button in the corresponding properties dialog, all open operator properties dialogs are updated. (9646)

In metadata parameters, empty parameter values are allowed now. No warning will be displayed. (4882)

The documentation for operator RGB2HSI now names the color space conversion the operator actually carries out: The operator implements the RGB to HSL (Hue Saturation Luminance) color space conversion, and NOT RGB to HSI (Hue Saturation Intensity) or RGB to HSV (Hue Saturation Value).