Operator MULT

Operator Library: Arithmetics

Operator MULT multiplies the values at input link I1 by the values at input link I2. At output link O, the result of the multiplication is provided.

Operator MULT supports asymmetric arithmetic types on its inputs, i.e., SIGNED and UNSIGNED may be mixed up so that you can multiply an unsigned multiplier with a signed multiplicand or a signed multiplier with an unsigned multiplicand as well as a signed multiplier with a signed multiplicand or an unsigned multiplier with an unsigned multiplicand.

[Note] Resources

A multiplication requires many FPGA resources. For scaling with a constant use operator SCALE or ShiftLeft instead. Moreover, most frame grabbers include embedded arithmetic logic units (embedded multipliers). Use operator HWMULT to save resources.

I/O Properties

Property Value
Operator Type O
Input Links I1, multiplicand 1
I2, multiplicand 2
Output Link O, multiplication result

Supported Link Format

Link Parameter Input Link I1 Input Link I2 Output Link O
Bit Width [1, 32] unsigned, [2, 32] signed [1, 32] unsigned, [2, 32] signed auto1
Arithmetic {unsigned, signed} {unsigned, signed} {unsigned, signed}2
Parallelism any as I1 as I1
Kernel Columns any as I1 as I1
Kernel Rows any as I1 as I1
Img Protocol {VALT_IMAGE2D, VALT_LINE1D, VALT_PIXEL0D} as I1 as I1
Color Format VAF_GRAY as I1 as I1
Color Flavor FL_NONE as I1 as I1
Max. Img Width any as I1 as I1
Max. Img Height any as I1 as I1

1

The output bit width is the sum of the input bit widths i.e. bit width at I1 + bit width at I2.

2

If I1 or I2 is set to signed, O must be set to signed as well.

Parameters

None

Examples of Use

The use of operator MULT is shown in the following examples: