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VisualApplets

Table of Contents

User Manual

Introduction

VisualApplets
How to Use This Documentation
System Requirements

Getting Started

Writing Your First Applet
Running Your Applet on Hardware
Further Reading

Basic Functionality

Basic Principles
Workflow
Main Program Window
Entering a Design
Data Flow
Rules of Links
Diagram Parametrization
Allocation of Device Resources
Design Rules Check
Simulation
FPGA Resource Estimation
Build
Framegrabber SDK

Extended Functionality

Hierarchical Boxes
User Libraries
Custom Operator Libraries
Multiple Processes
Target Hardware Porting
PixelPlant Designs
System Settings
Design Settings
Build Settings
Tcl Scripting
Script Collection (Tcl)
Tcl Export
Print / Screenshot
Migration from Older Versions

Embedded VisualApplets (eVA)

Introduction
Common Interfaces for all Platforms
Defining the IP Core Properties
Embedding and Simulating the IP core
Runtime Software Interface
Licensing Model
Application Notes

Miscellaneous

Command Line Options
Keyboard Shortcuts
Error Reporting

Tutorial and Examples

Introduction

Hardware Applet: From Idea to Application

Workflow Description
Designing an Applet in VisualApplets
Building the Applet in VisualApplets
Running the Applet on Hardware

Basic Design Theory

Applet Parameterization
Multiple DMA Channel Designs
Synchronization of Asynchronous Image Pipelines

Basic Acquisition Designs for Varying Camera Types and Hardware Platforms

Basic Acquisition Examples for Camera Link Cameras for microEnable IV VD4-CL/-PoCL Frame Grabber
Basic Acquisition Examples for GigE Vision Cameras for microEnable IV Frame Grabber
Basic Acquisition Examples for Camera Link Cameras for marathon, LightBridge and ironman Frame Grabbers
Basic Acquisition Examples for CoaXPress Cameras for marathon and ironman Frame Grabbers
Basic Acquisition Examples for Cameras for CoaXPress 12 imaFlex Frame Grabber

imaFlex CXP-12 Quad Implementation Examples

Functional Example for Operator ImageBufferMultRoi on imaFlex CXP-12 Quad Platform
Functional Example for Operator ImageBufferMultRoiDyn on imaFlex CXP-12 Quad Platform
Functional Example for Loading Test Images Using ImageInjector
Functional Example for Multi Tap Camera Interface with Tap Geometry Sorting
Functional Example for User Lib Operator JPEG_Encoder_Color_iF on imaFlex CXP-12 Quad Platform

Processing Examples

Advanced
Binarization
Blob Analysis
Color
Co-Processor
Debugging and Test
Difference Images
Filter
Geometry
High Dynamic Range and Image Composition
Lookup Tables
Loop
Object Features
Shading Correction
Trigger

Operator Examples

Functional Example for Specific Operators of Library Accumulator and Library Logic
Functional Example for Specific Operators of Library Synchronization: Dynamic Append and Cut
Functional Example for Specific Operators of Library Memory and Library Signal
Functional Example for Specific Operators of Library Memory and Library Signal
Functional Example for Specific Operators of Library Signal
Functional Example for Specific Operators of Library Synchronization, Base and Filter
Functional Example for Specific Operators of Library Arithmentics: Trigonometric Functions
Functional Example for Specific Operators of Library Color, Base and Memory
Functional Example for Specific Operators of Library Signal, Logic, Filter and Parameters

Parameter Library Examples

Parameter Redirection
Parameter Translation
User Library Parameter
Parameter Selection
Link Parameter Translation

Using Applets During Runtime

Filling LUT with Content With the Basler Framegrabber API

Operator Reference

Introduction

Library Overview

Library Accumulator

ColMax
ColMin
ColSum
Count
FrameMax
FrameMin
FrameSum
Histogram
ModuloCount
Register
RowMax
RowMin
RowSum

Library Arithmetics

ABS
ADD
ARCCOS
ARCCOT
ARCSIN
ARCTAN
ClipHigh
ClipLow
COS
COT
DIV
MULT
RND
SCALE
ShiftLeft
ShiftRight
SIN
SQRT
SUB
TAN

Library Base

Library Blob

Definition
Definition of Object Features
VisualApplets Operators
Blob_Analysis_1D
Blob_Analysis_2D

Library Color

BAYER3x3Linear
BAYER5x5Linear
ColorTransform
HSI2RGB
RGB2HSI
RGB2YUV
WhiteBalance
WhiteBalanceBayer

Library Compression

ImageBuffer_JPEG_Gray
JPEG_Encoder_Gray
JPEG_Encoder

Library Debugging

ImageAnalyzer
ImageStatistics
StreamAnalyzer
Scope
ImageInjector
ImageTimingGenerator
ImageFlowControl
StreamControl
ImageMonitor

Library Filter

DILATE
ERODE
FIRkernelNxM
FIRoperatorNxM
HitOrMiss
LineNeighboursNx1
MAX
MEDIAN
MIN
NumberOfHits
PixelNeighbours1xM
SORT

Library Logic

AND
CASE
CMP_AgeB
CMP_AgtB
CMP_AleB
CMP_AltB
CMP_Equal
CMP_NotEqual
IF
IS_Equal
IS_GreaterEqual
IS_GreaterThan
IS_InRange
IS_LessEqual
IS_LessThan
IS_NotEqual
NOT
OR
XNOR
XOR

Library Memory

CoefficientBuffer
FrameBufferRandomRead
FrameMemory
FrameMemoryRandomRd
FrameBufferRandomRead (imaFlex)
ImageBuffer
ImageBufferMultiRoI
ImageBufferMultiRoIDyn
ImageBufferSC
ImageBufferSpatial
ImageFifo
ImageSequence
KneeLUT
LineBuffer (imaFlex)
LineMemory
LineMemoryRandomRd
LUT
RamLUT
RamLUT (imaFlex)
ROM

Library Parameters

EnumParamReference
EnumParamTranslator
EnumVariable
FloatFieldParamReference
FloatParamReference
FloatParamTranslator
FloatVariable
IntFieldParamReference
IntParamReference
IntParamTranslator
IntVariable
LinkProperties
LinkParamTranslator
StringParamReference
ResourceReference
IntParamSelector
FloatParamSelector

Library Hardware Platform

Library Prototype

COUNTER
CustomSignalOperator
HWMULT
PackbitsRLE
TrgBoxLine
RGB2XYZ
XYZ2LAB

Library Signal

Library Synchronization

AppendImage
AppendImageDyn
AppendLine
AppendLineDyn
CutImage
CutLine
CreateBlankImage
ExpandLine
ExpandPixel
ImageValve
InsertImage
InsertLine
InsertPixel
IsFirstPixel
IsLastPixel
PixelReplicator
PixelToImage
RemoveImage
RemoveLine
RemovePixel
ReSyncToLine
RxImageLink
SourceSelector
SplitImage
SplitLine
SYNC
TxImageLink
Overflow

Library Transformation

FFT

Appendix. Device Resources

Hardware Configuration of Supported Platforms
Device Resources of Supported Platforms
Shared Memory Concept

Bibliography

List of Figures

1. VisualApplets - From Idea to Image Processor in 15 Minutes
2. VisualApplets – Awarded Software Environment
3. VisualApplets Main Window
4. Start of a New Project
5. Dragging Operators from Libraries into the Design Window
6. Module Properties
7. Successful DRC
8. Build Settings for microEnable 5 / Xilinx Vivado
9. Simple VisualApplets Design
10. The Design Workflow
11. Main Program Window
12. Operator not available for currently selected target hardware platform
13. Project Info
14. Module Search
15. Module Search
16. Parameter Info
17. DRC Log Information
18. Build Log Information
19. Example: Displaying Information on the MergeKernel Operator
20. Library Panel with Operator Library on Display
21. Library Panel with Operator Library on Display
22. Configuring the number of displayed recent designs
23. Start of a new Project
24. Edit Project Details
25. Menu Design, menu item Change FPGA Clock
26. Slider and spin box for selecting FPGA clock frequency
27. Operator Libraries
28. Error message in case an operator is not applicable for another hardware platform
29. Simple VisualApplets Design
30. Pixel Order
31. Model of a 2D Image Protocol
32. Model of a 1D Image Protocol
33. Model of an 0D Image Protocol
34. O-Type Network
35. Failing O-Type Network
36. Display of not correctly synchronized data flow in VisualApplets 2.2 and higher
37. M-type and O-type Network
38. M-type Operator with One Synchronous Input Group
39. M-type Operator with Asynchronous Inputs
40. Synchronization of Independent Sources
41. Deadlock at SYNC, figure a
42. Deadlock at SYNC, figure b
43. Fixed Deadlock
44. Deadlock Avoided
45. Bandwidth Limitation
46. Bandwidth Limitation Compensated
47. Infinite Source Connection Error
48. Infinite Source Connection OK
49. Infinite source conversion module (Buffer1) connected to a non-infinite source
50. O-type module with signal link inputs, sourced by different M-type modules
51. The Parameter Info View
52. Parameter Info
53. Module Properties Dialog
54. Field Parameter Edit Window
55. Function Dialog to Edit Field Parameters
56. Disabled Parameters
57. Parameters in Illegal States
58. Metadata Parameter
59. Invalid Source Port Link Properties
60. Invalid Destination Port Link Properties
61. Device Resource Allocation Window
62. Grayed-out resource CameraControl
63. Device Resource Conflict
64. Auto Correction of Device Resource Conflicts
65. DRC Level 1 Error
66. Creating New Simulation Sources and Probes
67. Simulation Sources Are Gray Image Frames, Simulation Probes Are Green Image Frames
68. Simulation Source Viewer
69. Viewing Options
70. Pixel Values
71. Zooming in the Magnifier
72. Thumbnail Display in Source
73. Highlighted Image Section Used for Simulation
74. sim[x] Indicates the Image that Is Simulated in a Sequence
75. Crosshair Cursors in Display Window and Magnifier
76. Pixel Values
77. Image Dimensions
78. Exceeded Image Dimensions
79. Bit Widths of Image and Link
80. Defining Offset for Image Bits to Use
81. Display Properties for 4-bit Image
82. Defining Offset for Link Bits to Use
83. Display Alignment
84. Pixel Merge
85. Merging Factor = 1, Image Properties Do Not Fit Link Properties
86. Merging Factor = 2, Properties of Merged Image Fit Link Properties
87. Simulation Window
88. Changing Source and Probe Display
89. Non-connected Simulation Modules
90. Simulation Settings
91. Second Simulation Step
92. Third Simulation Step
93. Successful Simulation
94. Pixel Values Probe
95. Display of Undefined Image Areas
96. Empty Image Symbol
97. Link View
98. Line Profile View
99. Line Histogram View
100. Image Histogram View
101. Save Options Dialog
102. File Format Options for Saving
103. Setting the Splitting Factor in the Save Options Dialog
104. Project Info Window
105. Detailed Information on FPGA Resource Estimation
106. Context Menu FPGA Resources
107. FPGA Resource Usage of Individual Module
108. Detected Xilinx tools
109. Selecting the Build Configuration for Applet Build
110. Target Runtime Selection during Applet Build
111. Build Setting for imaFlex CXP-12 Quad
112. Repacking Hardware Applet Files Window
113. Fullfilled Repacking Preconditions
114. Selecting Target Operating System
115. Display of Specified Repacking Settings
116. Message after Successful Repacking
117. Selecting the Storing Location for the SDK Example
118. Example of a Hierarchical Box
119. Window tabs of the design window
120. Highlighting a Port
121. Highlighting a Port
122. Entering a port name
123. Renamed ports of a hierarchical box
124. Highlighting a port
125. Reordered input ports of a hierarchical box
126. User Libraries with Elements in the Library Panel
127. Saving a Hierarchical Box as a User Library Element
128. Adding documentation, version information, short description, and/or individual GUI Icon
129. Providing a password for a library element
130. Tooltip Information on User Library Element
131. Display of Your Library Element in Design
132. Saving New User Library Element
133. Adding documentation, version information, short description, and/or individual GUI Icon
134. Providing a password for a library element
135. Tooltip Information on User Library Element
136.
137. Protecting a user library element
138. Entering password for protected user library element
139. Opening the User Library Editor
140. Replacement of Instances
141. Applet with Two Processes
142. Creating a New Process
143. Target Hardware Porting
144. Error message in case an operator is not applicable for new hardware platform
145. Dialog window for Path Settings
146. Dialog window for Simulation Settings
147. Example: If you always create applets for a Win64 system, you can set this operating system platform here as the default platform
148. Example: Win64 will be suggested by the program when you create a new applet design
149. Dialog window for Diagram Settings
150. Dialog window for Global Build Settings
151. Dialog window for common settings
152. Target Runtime Project Setting
153. Editing the Design Properties
154. Diagram Layout Settings
155. Selection of Hardware Platform
156. Build Settings Window
157. Vivado Supported by Target Hardware Design
158. Vivado not Supported by Target Hardware Design
159. Parameter Set Example: Developing for microEnable 5 or LightBridge
160. Defaut: All Build Flow Steps Activated
161. Subsequent Build Steps Deactivated
162. Keeping Build Files of the Individual Build Steps
163. Keeping Build Files of the Individual Build Steps
164. Command Mode Options
165. Command Mode "Use platform default value"
166. Command Mode "Append to platform default value"
167. Command Mode "Overwrite platform default value"
168. Handling Options
169. Script Collection in the VisualApplets program window
170. Exporting a Design
171. Importing a Design
172. Graphical Programming of Image Processing Applications on FPGAs
173. Once-Only Integration Process for new Hardware Platform
174. FPGA Design and IP Core Content as Building Blocks for Bitstream Generation
175. VisualApplets Program Window with Image Processing Design
176. Example for a Simple Image Acquisition Applet with Interface-Requiring Operators
177. Concept of VA IP Core Interfaces
178. Ports of the Register Interface
179. Example IP Core as specified for Zynq Platform
180. Port Layout for Image Input Interface
181. Waveform Illustrating the Protocol on an Image Input Port
182. Example of eVA IP Core
183. Port Layout for Image Output Interface
184. Waveform Illustrating the Protocol on an Image Output Port
185. Example of eVA IP Core
186. Port Layout for Memory Interface Where X Is the Index of the Interface Port
187. Waveform Illustrating the Memory Interface Protocol
188. Example of VA IP Core
189. Example Test Bench for IP Core with 1 ImgIn Interface, 1 ImgOut Interface, 1 Memory Interface, 1 GPI, 1 GPO, and Slave Interface
190. Circuit for Monitoring the Input Data Rate
191. Control Hierarchical Box
192. VisualApplets Main Window
193. New Project window
194. Operator Documentation in VisualApplets
195. Example Design Implementation Sobel_Filter.va
196. Link Properties
197. Static and Dynamic Operator Parameters
198. Design Rule Check 1 and 2 for the Example Design Sobel_Filter.va
199. FPGA Resource Estimation
200. Build Hardware Applet Dialog
201. Firmware Partitions Displayed in microDiagnostics
202. Parameter Tree and Image Acquisition Window in microDisplay
203. Generated SDK Project Files
204. Properties of Operator CameraGrayAreaBase
205. Changed the Link Bit Width of the Camera Operator
206. Bit Width Cannot be Changed at Buffer Module Output Link
207. Illegal Condition after Link Property Change
208. DRC Error Messages Invalid Parameters
209. Red Parameters show Illegal Condition
210. ConvertPixelFormat Operator Added for 16Bit Output
211. ShiftLeft Operator Added for 16Bit Output
212. Block Diagram of Threshold Binarization Design with Monitoring
213. Use of the Binarization Applet in microDisplay
214. VisualApplets design to switch between two cameras
215. Deadlock Configurations using InsertImage
216. Line Duplication
217. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode
218. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode
219. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode
220. Basic Acquisition for RGB Camera Link Area Scan Cameras in Medium Configuration Mode
221. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Full Configuration Mode
222. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Full Configuration 10 Bit Mode
223. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
224. Basic Acquisition for RGB Camera Link Line Scan Cameras in Base Configuration Mode
225. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Medium Configuration Mode
226. Basic Acquisition for Grayscale 12 Bit Camera Link Line Scan Cameras in Medium Configuration Mode
227. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Full Configuration Mode
228. Basic Acquisition for Grayscale GigE Vision Area Scan Cameras
229. Basic Acquisition for RGB GigE Vision Area Scan Cameras
230. Basic Acquisition for Grayscale GigE Vision Line Scan Cameras
231. Basic Acquisition for RGB GigE Vision Line Scan Cameras
232. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
233. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
234. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
235. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
236. Basic Acquisition Design for marathon VCL, LightBridge VCL and ironman VCL Frame Grabber for Camera Link Area Scan Cameras in Full Configuration Mode
237. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
238. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode on the LightBridge VCL, marathon VCL and ironman VCL
239. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
240. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
241. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
242. Basic Acquisition for marathon, LightBridge and ironman Frame Grabber for Camera Link Line Scan Cameras in Full Configuration Mode
243. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
244. Basic Acquisition for RGB CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
245. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
246. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the marathon Frame Grabber
247. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
248. Basic Acquisition for RGB CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
249. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
250. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
251. Basic Acquisition for One Grayscale CoaxPress Area Scan Camera with Link Aggregation 4 on the imaFlex Frame Grabber
252. Basic Acquisition for Four CoaXPress12 Single Link Area Scan Cameras
253. Basic Acquisition Example for Multiple Bit Widths on imaFlex Platform
254. Basic Acquisition Example for Color Format Support on imaFlex Platform
255. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras on the imaFlex Frame Grabber
256. Sinewave
257. FFT Result
258. FFT Result
259. Basic design structure
260. Content of box JPEGBlockSorter8x8
261. Rearangement of Pixel in JPEGBlockSorter8x8
262. Content of SplitImage box
263. Content of the RemoveFillByte box
264. Content of the RestartMarker box
265. Basic design structure
266. Top level design structure
267. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder
268. Top level design structure
269. Basic implementation of color JPEG compression using user library elements
270. Artificial test image
271. Straight edge
272. Diagonal edge
273. Curved edge
274. Periodic structure
275. Bayer pattern
276. Basic design structure
277. Content of NearestNeighbour
278. Basic design structure
279. Content of HierarchicalBox Laplace
280. Content of HierarchicalBox SortToComponents
281. Basic design structure
282. Interpolation step 1 of the Bayer-demosaicing process
283. Content of ColourInterpolation
284. Content of the HierarchicalBox BlueAndRed
285. Original color image
286. Image demosaiced with the algorithm of Laroche et al. [Lar94]
287. Image demosaiced with an bilinear $\text{[math]}$ algorithm
288. Content of ColourInterpolation for the modified Laroche filter.
289. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByGreen_GreenFollowedByBlue/Red
290. Basic design structure of "BilinearBayer_RG_GB.va"
291. Content of HierarchicalBox DeBayer
292. Content of HierarchicalBox DeBayerEnhancedRAW
293. Kernel components created in HierarchicalBox MakeKernel
294. Content of HierarchicalBox DeBayerRAW
295. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByBlue/Red_GreenFollowedByGreen
296. Basic design structure of "BilinearBayer_RB_GG.va"
297. Content of HierarchicalBox DeBayer
298. Content of HierarchicalBox DeBayerEnhanced
299. Kernel components selected in HierarchicalBox DeBayerEnhanced by operator SelectSubKernel3x2
300. Content of HierarchicalBox DeBayerFast
301. Pre-Sorting of Color Components
302. Simulation Result of Pre-Sorted Color Components
303. Parameter Setting for XOffset of the ImageBufferMultiRoI Operator
304. Pre-Sorting for Color Separation by collecting eight successive pixel of the same component.
305. Color Separation with FrameBufferRandomRead
306. Address Generator for FrameBufferRandomRead Input
307. Block Diagram of the applet Hardware Test
308. Hardware Test Process0
309. Hardware Test Process1
310. Applet Hardware Test use of Parameter Translates and References in microDisplay
311. Applet Hardware Test Implementation for RAM Test, DMA Perfomance Test and Camera Acquisition
312. Use of FloatParamTranslator to Convert from Frames per Second to Ticks
313. Use of IntParamTranslator for easy Setting of the Width and Height in the Applet
314. Basic design structure of the VA design "TriggerAndImageStatistics.va"
315. Content of HierarchicalBox TriggerAnalysis
316. Content of HierarchicalBox CameraLink_InputStatistics
317. Content of HierarchicalBox Trigger_Statistics
318. Content of HierarchicalBox DelayAnalysis
319. Content of HierarchicalBox ImageAnalysis
320. Basic design structure of the VA design "GeometricTransformation_FrameBufferRandomRead.va"
321. Content of HierarchicalBox"GeometricTransformation"
322. Content of HierarchicalBox CoordinateTransformation
323. Content of HierarchicalBox OutputImage
324. Content of HierarchicalBox InverseTransformation
325. Source image [Ope16a]
326. Rotated and translated target image
327. Basic design structure of the VA design "GeometricTransformation_ImageMoments.va"
328. Content of the HierarchicalBox GeometricTransformation
329. Content of HierarchicalBox CoordinateTransformation
330. Content of HierarchicalBox InverseTransformation
331. Content of HierarchicalBox GeometricTransformation
332. Source image (dimension: 640x240 pixels)
333. Position and orientation corrected target image (dimension: 256x128 pixels)
334. Example: 8 Pixels are stored in one DRAM cell
335. Content of HierarchicalBox FrameBufferRandomRead_Par8
336. Basic design structure of the VA design "GeometricTransformation_DistortionCorrection.va"
337. Content of HierarchicalBox CoordinateTransformation
338. Content of HierarchicalBox KeystoneCorrection
339. Content of HierarchicalBox DistortionCorrection
340. Content of HierarchicalBox DistortionCoefficient
341. Example Source Image [Ope16a]
342. Distortion and Keystone corrected target image
343. Rotated, distortion and Keystone corrected target image
344. Basic design structure of the VA design "DistortionCorrection.va"
345. Content of HierarchicalBox DistortionCorrection
346. Content of HierarchicalBox InverseCorrection
347. Basic design structure
348. Content of ImageMoments
349. Content of the HierarchicalBox orientation_theta
350. Content of the HierarchicalBox eccentricity
351. Skew of a scanned object resulting from camera misalignment
352. Basic design structure
353. Content of HierarchicalBox LineShear
354. Content of HierarchicalBox ExtractInteger
355. Content of HierarchicalBox Select
356. Content of HierarchicalBox TransformedYCoordinate
357. Shift corrected image
358. Basic design structure for scaling a line camera image
359. Components of Transformation
360. Components of WordToRead
361. Components of PixelPicker
362. Content of Pick_0
363. Components of Interpolation
364. Basic design structure for "TapSorting_2XE_1Y.va"
365. Basic design structure of "TapSorting_2X_2Y.va"
366. Content of the HierarchicalBox Address in "TapSorting_2X_2Y.va"
367. Basic design structure of "TapSorting_8X_1Y.va"
368. Content of the HierarchicalBox Sorting_8X_1Y
369. Content of the HierarchicalBox Address in "TapSorting_8X_1Y.va"
370. Basic design structure
371. Content of box Trigger
372. Content of box HDR
373. Content of component Red in Image1
374. Content of box Red under HDR
375. Content of box LDR in the designs "HDR_CRC_Bayer.va" and "HDR_CRC_Color.va"
376. Content of box LDR in the design "HDR_CRC_Gray.va"
377. Basic design structure
378. Content of box HDR
379. Content of Red in box Image1
380. Content of Red in box HDR
381. Basic design structure of "ExposureFusion.va"
382. Content of HierarchicalBox ExposureFusion
383. Content of HierarchicalBox ImageComposition
384. Content of HierarchicalBox Weight
385. Content of HierarchicalBox Red in box Weight
386. Content of HierarchicalBox Red in box ImageComposition
387. Example input images with different exposure times
388. Result image of the 5 example input images after exposure fusion
389. Basic design structure
390. Content of HierarchicalBox DepthFromFocus
391. Content of HierarchicalBox CompareContrast
392. Content of HierarchicalBox SelectDepthIndex
393. Content of HierarchicalBox SelectPixelValue
394. Content of HierarchicalBox LastImageOfSequenceOnly
395. Basic Design structure of the VA designs "HOG_9Bins_Histogram.va","HOG_9Bins_HistogramMax.va" and "HOG_4Bins_HistogramMax.va"
396. Content of HierarchicalBiox HOG
397. Content of HierarchicalBox GradientFilter
398. Content of HierarchicalBox MagnitudeOrientation
399. Content of HierarchicalBox Histogram
400. Content of HierarchicalBox Bin1
401. Content of HierarchicalBox ConcatenateWithNeighbors
402. Content of HierarchicalBox GetHistogramMax
403. Basic design structure of the VA design "PrintInspection_Blob.va"
404. Content of the HierarchicalBox FindPatterns
405. Content of the HierarchicalBox ExtractCandidates
406. Content of the HierarchicalBox DetermingCOGTemplates
407. Content of the HierarchicalBox TemplateMatching
408. Content of the HierarchicalBox COG_Angle
409. Basic design structure of the VA design "PrintInspection_ImageMoments.va"
410. Basic design structure of "NormalizedCrossCorrelation.va"
411. Test image "PCB.tif"
412. Content of HierarchicalBox NCC
413. Content of HierarchicalBox Division
414. result image with "1" at object positions (zoomed view)
415. Hierarchical Box ImageTrigger of the TrgPortLine Rebuild Example
416. Hierarchical Box LineTrigger of the TrgPortLine Rebuild Example
417. Objects Visualized by Colored Boxes
418. 4-Connected Neighborhood
419. 8-Connected Neighborhood
420. Pixels allocated to objects in a 4-connected neighborhood (left) and an 8-connected neighborhood (right). All colored pixels represent foreground pixels where their allocation to objects is visualized by differing colors.
421. 4-connected neighborhood: Contour Orthogonal = 30, Diagonal = 0
422. 8-connected neighborhood: Contour Orthogonal = 14, Diagonal = 8
423. Calculation of the perimeter using an 8-connected neighborhood (left) and a 4-connected neighborhood (right)
424. Blob Analysis Operators
425. Behavior of the Blob Analysis 1D Operator
426. Synchronization of the Blob 1D Operator in a VisualApplets Network
427. Blob 1D Timing - Generation of New Frames
428. Blob 1D Timing - Suppression of Empty Frames
429. Blob 1D Timing - Constant Flush
430. Blob 1D Timing - Discarding of Objects
431. Simulation Scenario 1 - Flush and Y0 Relation
432. Simulation Scenario 2 - Flush Pixel Position
433. Simulation Scenario 3 - Discarded Flush Pixel at End of Frame
434. Simulation Scenario 4 - Multiple Blobs
435. Formula for calculating the minimum input image width
436. Overflow Event Data
437. Parameters for imaFlex CXP-12 Quad
438. Parameters for mE5 marathon, mE5 ironman and LightBridge VCL Platforms
439. Parameters for imaFlex CXP-12 Quad
440. Parameters for mE5 marathon, mE5 ironman and LightBridge VCL Platforms
441. This configuration is equivalent to a simpler CxpCamera operator with only O output and no meta data.
442. This configuration is equivalent to a simpler CxpCamera operator with port O and MetaDataO selected.
443. In this configuration only the tap 0 is output with its metadata. For the tap 1 only the metadata is output. This configuration can be useful for debugging a camera/frame grabber combination.
444. In this configuration the operator provides both camera taps as 2 separate data streams on its Tap0 and Tap1 ports. However, no metadata information is output.
445. In this configuration the operator provides both camera taps as 2 separate streams on its Tap0 and Tap1 ports. The operator provides also the meta information for the Tap0 port. This configuration might be meaningful for symmetrical camera tap configurations, where the CXP header is in most parts identical for both taps except for the TapG Code fields.
446. This is the maximal configuration of the operator, where for each tap an own output is presented together with its own metadata.
447. RAM architecture

List of Tables

1. Operator Types
2. List of Device Resources
3. Operator/Info
4. Operator/IO
5. Operator/Properties
6. Operator/ImgIn
7. Operator/ImgOut
8. Operator/RegIn
9. Operator/RegOut
10. Operator/Mem
11. Operator/Core
12. Commands for Creating and Editing a VA Design in Tcl
13. Command Line Options and According Arguments
14. Shortcut List for Main Program Window
15. Shortcut List for Simulation Viewer
16. List of Basic Acquisition Examples
17. Design Versions for Grayscale JPEG Encoding
18. Design Versions for Color JPEG Encoding
19. List of Bayer Demosaicing Examples
20. Overview of Color Separation Examples
21. List of Geometric Transformation Examples
22. Reading Cycles
23. Files and their corresponding lookup tables in Visual Applets
24. Examples of tap geometries
25. Available Libraries
26. Operators of Library Accumulator
27. Operators of Library Arithmetics
28. Operators of Library Base
29. Examples
30. Explanation of pseudo-code
31. Examples
32. Examples
33. Operators of Library Blob
34. Explanation of Blob Error Flags
35. Explanation of Blob Error Flags
36. Operators of Library Color
37. Operators of Library Compression
38. Operators of Library Debugging
39. Operators of Library Filter
40. Operators of Library Logic
41. Memory Types of Operators in the Library Memory
42. Individual Latencies of the Operators in Library Memory
43. Operators of Library Memory
44. Data types supported by reference operators
45. Operators of Library Parameters
46. Basic operations
47. Functions
48. Basic operations
49. Functions
50. Basic operations
51. Functions
52. Operators of Library Hardware Platform
53. Mapping VA notation and CL Specification Version 2.1
54. Mapping VA notation and CL Specification Version 2.1
55. Mapping VA notation and CL Specification Version 2.1
56.
57.
58.
59.
60. Operators of Library Prototype
61. Operators of Library Signal
62. Operators of Library Synchronization
63. Operators of Library Transformation
64. Hardware Configuration microEnable IV and PixelPlant
65. Hardware Configuration microEnable 5 ironman
66. Hardware Configuration LightBridge and microEnable 5 marathon
67. Hardware Configuration imaFlex CXP-12 Quad
68. List of Device Resources microEnable IV and PixelPlant
69. List of Device Resources microEnable 5 ironman
70. List of Device Resources LightBridge and microEnable 5 marathon
71. List of Device Resources IimaFlex CXP-12 Quad

List of Equations

1. Overlay Blend
2. Optimized Overlay Blend for FPGA Implementation

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