The basic principles of VisualApplets are very simple.
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Image processing or signal processing functions are represented by abstract operators.
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Operators are selected in accordance with the intended functionality of the applet. They can be chosen from extensive libraries.
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The operators are inserted into the user's design. The instance of an operator in a design is called module.
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A data flow model which represents the processing chain is build by linking modules.
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All modules and links can be parametrized to meet the requirements of the user's application and make the implementation fast and efficient.
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After successful offline verification, the design is built into a hardware applet file which can be loaded onto the hardware devices.
The following figure shows a screen shot of a simple VisualApplets design. As you can see, the modules in the design window are combined via links which are represented by arrows. The order of the modules define the functionality of the final applet. In this example, we acquire images from a camera (module Camera), buffer the images in an on-board memory (Buffer), and output the result to the host PC using the operator DmaToPC.
After all operators have been placed into a design, have been connected using links and parametrized, the design has to be verified. The program offers multiple functionalities to check consistency, bandwidth, and resources. One very important part of the verification is the functional simulation. Here, the design can be simulated with data from image files without the need of any target hardware.
Finally, the design is build to become a hardware applet file (HAP) which can be used on the target hardware devices. The next section will outline the workflow in detail.
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