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VisualApplets

Table of Contents

User Manual

Introduction

VisualApplets
How to Use This Documentation
System Requirements

Getting Started

Writing Your First Applet
Running Your Applet on Hardware
Further Reading

Basic Functionality

Basic Principles
Workflow
Main Program Window
Entering a Design
Data Flow
Rules of Links
Diagram Parametrization
Allocation of Device Resources
Design Rules Check
Simulation
FPGA Resource Estimation
Build
Framegrabber SDK

Extended Functionality

Hierarchical Boxes
User Libraries
Custom Operator Libraries
Multiple Processes
Target Hardware Porting
PixelPlant Designs
System Settings
Design Settings
Build Settings
Tcl Scripting
Script Collection (Tcl)
Tcl Export
Print / Screenshot
Migration from Older Versions

Embedded VisualApplets (eVA)

Introduction
Common Interfaces for all Platforms
Defining the IP Core Properties
Embedding and Simulating the IP core
Runtime Software Interface
Licensing Model
Application Notes

Miscellaneous

Command Line Options
Keyboard Shortcuts
Error Reporting

Tutorial and Examples

Introduction

Hardware Applet: From Idea to Application

Workflow Description
Designing an Applet in VisualApplets
Building the Applet in VisualApplets
Running the Applet on Hardware

Basic Design Theory

Applet Parameterization
Multiple DMA Channel Designs
Synchronization of Asynchronous Image Pipelines

Basic Acquisition Designs for Varying Camera Types and Hardware Platforms

Basic Acquisition Examples for Camera Link Cameras for microEnable IV VD4-CL/-PoCL Frame Grabber
Basic Acquisition Examples for GigE Vision Cameras for microEnable IV Frame Grabber
Basic Acquisition Examples for Camera Link Cameras for marathon, LightBridge and ironman Frame Grabbers
Basic Acquisition Examples for CoaXPress Cameras for marathon and ironman Frame Grabbers
Basic Acquisition Examples for Cameras for CoaXPress 12 imaFlex Frame Grabber

imaFlex CXP-12 Quad and Penta Implementation Examples

Functional Example for the FrameBufferMultRoiDyn Operator on the imaFlex CXP-12 Penta Platform
Functional Example for the FrameBufferMultRoi User Library Element on the imaFlex CXP-12 Penta Platform
Functional Example for the FrameBufferMultRoi User Library Element on the imaFlex CXP-12 Quad Platform
Functional Example for Loading Test Images Using ImageInjector
Functional Example for Multi Tap Camera Interface with Tap Geometry Sorting
Functional Example for the JPEG_Encoder_Color_iF User Library Element on the imaFlex CXP-12 Quad Platform
Functional Example for the JPEG_Encoder_Color_iF_Penta User Library Element on the imaFlex CXP-12 Penta Platform
Example for the DMAFromPC Operator on the imaFlex CXP-12 Quad Platform

Processing Examples

Advanced
Binarization
Blob Analysis
Color
Co-Processor
Debugging and Test
Difference Images
Filter
Geometry
High Dynamic Range and Image Composition
Lookup Tables
Loop
Object Features
Shading Correction
Trigger

Operator Examples

Functional Example for Specific Operators of Library Accumulator and Library Logic
Functional Example for Specific Operators of Library Synchronization: Dynamic Append and Cut
Functional Example for Specific Operators of Library Memory and Library Signal
Functional Example for Specific Operators of Library Memory and Library Signal
Functional Example for Specific Operators of Library Signal
Functional Example for Specific Operators of Library Synchronization, Base and Filter
Functional Example for Specific Operators of Library Arithmentics: Trigonometric Functions
Functional Example for Specific Operators of Library Color, Base and Memory
Functional Example for Specific Operators of Library Signal, Logic, Filter and Parameters

Parameter Library Examples

Parameter Redirection
Parameter Translation
User Library Parameter
Parameter Selection
Link Parameter Translation

Using Applets During Runtime

Filling LUT with Content With the Basler Framegrabber API

Operator Reference

Introduction

Library Overview

Library Accumulator

ColMax
ColMin
ColSum
Count
FrameMax
FrameMin
FrameSum
Histogram
ModuloCount
Register
RowMax
RowMin
RowSum

Library Arithmetics

ABS
ADD
ARCCOS
ARCCOT
ARCSIN
ARCTAN
ClipHigh
ClipLow
COS
COT
DIV
MULT
RND
SCALE
ShiftLeft
ShiftRight
SIN
SQRT
SUB
TAN

Library Base

Library Blob

Definition
Definition of Object Features
VisualApplets Operators
Blob_Analysis_1D
Blob_Analysis_2D

Library Color

BAYER3x3Linear
BAYER5x5Linear
ColorTransform
HSI2RGB
RGB2HSI
RGB2YUV
WhiteBalance
WhiteBalanceBayer

Library Compression

ImageBuffer_JPEG_Gray
JPEG_Encoder_Gray
JPEG_Encoder

Library Debugging

ImageAnalyzer
ImageStatistics
StreamAnalyzer
Scope
ImageInjector
ImageTimingGenerator
ImageFlowControl
StreamControl
ImageMonitor

Library Filter

DILATE
ERODE
FIRkernelNxM
FIRoperatorNxM
HitOrMiss
LineNeighboursNx1
MAX
MEDIAN
MIN
NumberOfHits
PixelNeighbours1xM
SORT

Library Logic

AND
CASE
CMP_AgeB
CMP_AgtB
CMP_AleB
CMP_AltB
CMP_Equal
CMP_NotEqual
IF
IS_Equal
IS_GreaterEqual
IS_GreaterThan
IS_InRange
IS_LessEqual
IS_LessThan
IS_NotEqual
NOT
OR
XNOR
XOR

Library Memory

CoefficientBuffer
FrameBufferMultiRoiDyn
FrameBufferRandomRead
FrameBufferRandomRead (imaFlex)
FrameMemory
FrameMemoryRandomRd
ImageBuffer
ImageBufferMultiRoI
ImageBufferMultiRoIDyn
ImageBufferSC
ImageBufferSpatial
ImageFifo
ImageSequence
KneeLUT
LineBuffer (imaFlex)
LineMemory
LineMemoryRandomRd
LUT
RamLUT
RamLUT (imaFlex)
ROM

Library Parameters

EnumParamReference
EnumParamTranslator
EnumVariable
FloatFieldParamReference
FloatParamReference
FloatParamTranslator
FloatVariable
IntFieldParamReference
IntParamReference
IntParamTranslator
IntVariable
IntFieldVariable
LinkProperties
LinkParamTranslator
StringParamReference
ResourceReference
IntParamSelector
FloatParamSelector

Library Hardware Platform

Library Prototype

COUNTER
CustomSignalOperator
HWMULT
PackbitsRLE
TrgBoxLine
RGB2XYZ
XYZ2LAB

Library Signal

Library Synchronization

AppendImage
AppendImageDyn
AppendLine
AppendLineDyn
CutImage
CutLine
CreateBlankImage
ExpandLine
ExpandPixel
ImageValve
InsertImage
InsertLine
InsertPixel
IsFirstPixel
IsLastPixel
PixelReplicator
PixelToImage
RemoveImage
RemoveLine
RemovePixel
ReSyncToLine
RxImageLink
SourceSelector
SplitImage
SplitLine
SYNC
TxImageLink
Overflow

Library Transformation

FFT

Appendix. Device Resources

Hardware Configuration of Supported Platforms
Device Resources of Supported Platforms
Shared Memory Concept

Bibliography

List of Figures

1. VisualApplets - From Idea to Image Processor in 15 Minutes
2. VisualApplets – Awarded Software Environment
3. VisualApplets Main Window
4. Start of a New Project
5. Dragging Operators from Libraries into the Design Window
6. Module Properties
7. Successful DRC
8. Build Settings for microEnable 5 / Xilinx Vivado
9. Simple VisualApplets Design
10. The Design Workflow
11. Main Program Window
12. Operator not available for currently selected target hardware platform
13. Project Info
14. Module Search
15. Module Search
16. Parameter Info
17. DRC Log Information
18. Build Log Information
19. Example: Displaying Information on the MergeKernel Operator
20. Library Panel with Operator Library on Display
21. Library Panel with Operator Library on Display
22. Configuring the number of displayed recent designs
23. Start of a new Project
24. Edit Project Details
25. Menu Design, menu item Change FPGA Clock
26. Slider and spin box for selecting FPGA clock frequency
27. Operator Libraries
28. Error message in case an operator is not applicable for another hardware platform
29. Simple VisualApplets Design
30. Pixel Order
31. Model of a 2D Image Protocol
32. Model of a 1D Image Protocol
33. Model of an 0D Image Protocol
34. O-Type Network
35. Failing O-Type Network
36. Display of not correctly synchronized data flow in VisualApplets 2.2 and higher
37. M-type and O-type Network
38. M-type Operator with One Synchronous Input Group
39. M-type Operator with Asynchronous Inputs
40. Synchronization of Independent Sources
41. Deadlock at SYNC, figure a
42. Deadlock at SYNC, figure b
43. Fixed Deadlock
44. Deadlock Avoided
45. Bandwidth Limitation
46. Bandwidth Limitation Compensated
47. Infinite Source Connection Error
48. Infinite Source Connection OK
49. Infinite source conversion module (Buffer1) connected to a non-infinite source
50. O-type module with signal link inputs, sourced by different M-type modules
51. The Parameter Info View
52. Parameter Info
53. Module Properties Dialog
54. Field Parameter Edit Window
55. Function Dialog to Edit Field Parameters
56. Disabled Parameters
57. Autocompletion for Reference Parameters
58. Autocompletion in "Enter data for <operator>/<parameter> Dialog
59. Syntax Highlighting in "Enter data for <operator>/<parameter> Dialog
60. Syntax Highlighting in Module Properties Dialog
61. Autocompletion for Translator Operators
62. Parameters in Illegal States
63. Metadata Parameter
64. Invalid Source Port Link Properties
65. Invalid Destination Port Link Properties
66. Device Resource Allocation Window
67. Grayed-out resource CameraControl
68. Device Resource Conflict
69. Auto Correction of Device Resource Conflicts
70. DRC Level 1 Error
71. Creating New Simulation Sources and Probes
72. Simulation Sources Are Gray Image Frames, Simulation Probes Are Green Image Frames
73. Simulation Source Viewer
74. Viewing Options
75. Pixel Values
76. Zooming in the Magnifier
77. Thumbnail Display in Source
78. Highlighted Image Section Used for Simulation
79. sim[x] Indicates the Image that Is Simulated in a Sequence
80. Crosshair Cursors in Display Window and Magnifier
81. Pixel Values
82. Image Dimensions
83. Exceeded Image Dimensions
84. Bit Widths of Image and Link
85. Defining Offset for Image Bits to Use
86. Display Properties for 4-bit Image
87. Defining Offset for Link Bits to Use
88. Display Alignment
89. Pixel Merge
90. Merging Factor = 1, Image Properties Do Not Fit Link Properties
91. Merging Factor = 2, Properties of Merged Image Fit Link Properties
92. Simulation Window
93. Changing Source and Probe Display
94. Non-connected Simulation Modules
95. Simulation Settings
96. Second Simulation Step
97. Third Simulation Step
98. Successful Simulation
99. Pixel Values Probe
100. Display of Undefined Image Areas
101. Empty Image Symbol
102. Link View
103. Line Profile View
104. Line Histogram View
105. Image Histogram View
106. Save Options Dialog
107. File Format Options for Saving
108. Setting the Splitting Factor in the Save Options Dialog
109. Project Info Window
110. Detailed Information on FPGA Resource Estimation
111. Context Menu FPGA Resources
112. FPGA Resource Usage of Individual Module
113. Detected Xilinx tools
114. Selecting the Build Configuration for Applet Build
115. Target Runtime Selection during Applet Build
116. Build Setting for imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
117. Repacking Hardware Applet Files Window
118. Fullfilled Repacking Preconditions
119. Selecting Target Operating System
120. Display of Specified Repacking Settings
121. Message after Successful Repacking
122. Selecting the Storing Location for the SDK Example
123. Example of a Hierarchical Box
124. Window tabs of the design window
125. Highlighting a Port
126. Highlighting a Port
127. Entering a port name
128. Renamed ports of a hierarchical box
129. Highlighting a port
130. Reordered input ports of a hierarchical box
131. User Libraries with Elements in the Library Panel
132. Saving a Hierarchical Box as a User Library Element
133. Adding documentation, version information, short description, and/or individual GUI Icon
134. Providing a password for a library element
135. Tooltip Information on User Library Element
136. Display of Your Library Element in Design
137. Saving New User Library Element
138. Adding documentation, version information, short description, and/or individual GUI Icon
139. Providing a password for a library element
140. Tooltip Information on User Library Element
141.
142. Protecting a user library element
143. Entering password for protected user library element
144. Opening the User Library Editor
145. Replacement of Instances
146. Applet with Two Processes
147. Creating a New Process
148. Target Hardware Porting
149. Error message in case an operator is not applicable for new hardware platform
150. Dialog window for Path Settings
151. Dialog window for Simulation Settings
152. Example: If you always create applets for a Win64 system, you can set this operating system platform here as the default platform
153. Example: Win64 will be suggested by the program when you create a new applet design
154. Dialog window for Diagram Settings
155. Dialog window for Global Build Settings
156. Dialog window for common settings
157. Target Runtime Project Setting
158. Editing the Design Properties
159. Diagram Layout Settings
160. Selection of Hardware Platform
161. Build Settings Window
162. Vivado Supported by Target Hardware Design
163. Vivado not Supported by Target Hardware Design
164. Parameter Set Example: Developing for microEnable 5 or LightBridge
165. Defaut: All Build Flow Steps Activated
166. Subsequent Build Steps Deactivated
167. Keeping Build Files of the Individual Build Steps
168. Keeping Build Files of the Individual Build Steps
169. Command Mode Options
170. Command Mode "Use platform default value"
171. Command Mode "Append to platform default value"
172. Command Mode "Overwrite platform default value"
173. Handling Options
174. Script Collection in the VisualApplets program window
175. Exporting a Design
176. Importing a Design
177. Graphical Programming of Image Processing Applications on FPGAs
178. Once-Only Integration Process for new Hardware Platform
179. FPGA Design and IP Core Content as Building Blocks for Bitstream Generation
180. VisualApplets Program Window with Image Processing Design
181. Example for a Simple Image Acquisition Applet with Interface-Requiring Operators
182. Concept of VA IP Core Interfaces
183. Ports of the Register Interface
184. Example IP Core as specified for Zynq Platform
185. Port Layout for Image Input Interface
186. Waveform Illustrating the Protocol on an Image Input Port
187. Example of eVA IP Core
188. Port Layout for Image Output Interface
189. Waveform Illustrating the Protocol on an Image Output Port
190. Example of eVA IP Core
191. Port Layout for Memory Interface Where X Is the Index of the Interface Port
192. Waveform Illustrating the Memory Interface Protocol
193. Example of VA IP Core
194. Example Test Bench for IP Core with 1 ImgIn Interface, 1 ImgOut Interface, 1 Memory Interface, 1 GPI, 1 GPO, and Slave Interface
195. Circuit for Monitoring the Input Data Rate
196. Control Hierarchical Box
197. VisualApplets Main Window
198. New Project window
199. Operator Documentation in VisualApplets
200. Example Design Implementation Sobel_Filter.va
201. Link Properties
202. Static and Dynamic Operator Parameters
203. Design Rule Check 1 and 2 for the Example Design Sobel_Filter.va
204. FPGA Resource Estimation
205. Build Hardware Applet Dialog
206. Firmware Partitions Displayed in microDiagnostics
207. Parameter Tree and Image Acquisition Window in microDisplay
208. Generated SDK Project Files
209. Properties of Operator CameraGrayAreaBase
210. Changed the Link Bit Width of the Camera Operator
211. Bit Width Cannot be Changed at Buffer Module Output Link
212. Illegal Condition after Link Property Change
213. DRC Error Messages Invalid Parameters
214. Red Parameters show Illegal Condition
215. ConvertPixelFormat Operator Added for 16Bit Output
216. ShiftLeft Operator Added for 16Bit Output
217. Block Diagram of Threshold Binarization Design with Monitoring
218. Use of the Binarization Applet in microDisplay
219. VisualApplets design to switch between two cameras
220. Deadlock Configurations using InsertImage
221. Line Duplication
222. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode
223. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode
224. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode
225. Basic Acquisition for RGB Camera Link Area Scan Cameras in Medium Configuration Mode
226. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Full Configuration Mode
227. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Full Configuration 10 Bit Mode
228. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
229. Basic Acquisition for RGB Camera Link Line Scan Cameras in Base Configuration Mode
230. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Medium Configuration Mode
231. Basic Acquisition for Grayscale 12 Bit Camera Link Line Scan Cameras in Medium Configuration Mode
232. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Full Configuration Mode
233. Basic Acquisition for Grayscale GigE Vision Area Scan Cameras
234. Basic Acquisition for RGB GigE Vision Area Scan Cameras
235. Basic Acquisition for Grayscale GigE Vision Line Scan Cameras
236. Basic Acquisition for RGB GigE Vision Line Scan Cameras
237. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
238. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
239. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
240. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
241. Basic Acquisition Design for marathon VCL, LightBridge VCL and ironman VCL Frame Grabber for Camera Link Area Scan Cameras in Full Configuration Mode
242. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
243. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode on the LightBridge VCL, marathon VCL and ironman VCL
244. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
245. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
246. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
247. Basic Acquisition for marathon, LightBridge and ironman Frame Grabber for Camera Link Line Scan Cameras in Full Configuration Mode
248. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
249. Basic Acquisition for RGB CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
250. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
251. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the marathon Frame Grabber
252. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
253. Basic Acquisition for RGB CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
254. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
255. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
256. Basic Acquisition for One Grayscale CoaxPress Area Scan Camera with Link Aggregation 4 on the imaFlex Frame Grabber
257. Basic Acquisition for Four CoaXPress12 Single Link Area Scan Cameras
258. Basic Acquisition Example for Multiple Bit Widths on imaFlex Platform
259. Basic Acquisition Example for Color Format Support on imaFlex Platform
260. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras on the imaFlex Frame Grabber
261. Sinewave
262. FFT Result
263. FFT Result
264. Basic design structure
265. Content of box JPEGBlockSorter8x8
266. Rearangement of Pixel in JPEGBlockSorter8x8
267. Content of SplitImage box
268. Content of the RemoveFillByte box
269. Content of the RestartMarker box
270. Basic design structure
271. Top level design structure
272. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder
273. Top level design structure
274. Basic implementation of color JPEG compression using user library elements
275. Artificial test image
276. Straight edge
277. Diagonal edge
278. Curved edge
279. Periodic structure
280. Bayer pattern
281. Basic design structure
282. Content of NearestNeighbour
283. Basic design structure
284. Content of HierarchicalBox Laplace
285. Content of HierarchicalBox SortToComponents
286. Basic design structure
287. Interpolation step 1 of the Bayer-demosaicing process
288. Content of ColourInterpolation
289. Content of the HierarchicalBox BlueAndRed
290. Original color image
291. Image demosaiced with the algorithm of Laroche et al. [Lar94]
292. Image demosaiced with an bilinear $\text{[math]}$ algorithm
293. Content of ColourInterpolation for the modified Laroche filter.
294. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByGreen_GreenFollowedByBlue/Red
295. Basic design structure of "BilinearBayer_RG_GB.va"
296. Content of HierarchicalBox DeBayer
297. Content of HierarchicalBox DeBayerEnhancedRAW
298. Kernel components created in HierarchicalBox MakeKernel
299. Content of HierarchicalBox DeBayerRAW
300. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByBlue/Red_GreenFollowedByGreen
301. Basic design structure of "BilinearBayer_RB_GG.va"
302. Content of HierarchicalBox DeBayer
303. Content of HierarchicalBox DeBayerEnhanced
304. Kernel components selected in HierarchicalBox DeBayerEnhanced by operator SelectSubKernel3x2
305. Content of HierarchicalBox DeBayerFast
306. Pre-Sorting of Color Components
307. Simulation Result of Pre-Sorted Color Components
308. Parameter Setting for XOffset of the ImageBufferMultiRoI Operator
309. Pre-Sorting for Color Separation by collecting eight successive pixel of the same component.
310. Color Separation with FrameBufferRandomRead
311. Address Generator for FrameBufferRandomRead Input
312. Block Diagram of the applet Hardware Test
313. Hardware Test Process0
314. Hardware Test Process1
315. Applet Hardware Test use of Parameter Translates and References in microDisplay
316. Applet Hardware Test Implementation for RAM Test, DMA Perfomance Test and Camera Acquisition
317. Use of FloatParamTranslator to Convert from Frames per Second to Ticks
318. Use of IntParamTranslator for easy Setting of the Width and Height in the Applet
319. Basic design structure of the VA design "TriggerAndImageStatistics.va"
320. Content of HierarchicalBox TriggerAnalysis
321. Content of HierarchicalBox CameraLink_InputStatistics
322. Content of HierarchicalBox Trigger_Statistics
323. Content of HierarchicalBox DelayAnalysis
324. Content of HierarchicalBox ImageAnalysis
325. Basic design structure of the VA design "GeometricTransformation_FrameBufferRandomRead.va"
326. Content of HierarchicalBox"GeometricTransformation"
327. Content of HierarchicalBox CoordinateTransformation
328. Content of HierarchicalBox OutputImage
329. Content of HierarchicalBox InverseTransformation
330. Source image [Ope16a]
331. Rotated and translated target image
332. Basic design structure of the VA design "GeometricTransformation_ImageMoments.va"
333. Content of the HierarchicalBox GeometricTransformation
334. Content of HierarchicalBox CoordinateTransformation
335. Content of HierarchicalBox InverseTransformation
336. Content of HierarchicalBox GeometricTransformation
337. Source image (dimension: 640x240 pixels)
338. Position and orientation corrected target image (dimension: 256x128 pixels)
339. Example: 8 Pixels are stored in one DRAM cell
340. Content of HierarchicalBox FrameBufferRandomRead_Par8
341. Basic design structure of the VA design "GeometricTransformation_DistortionCorrection.va"
342. Content of HierarchicalBox CoordinateTransformation
343. Content of HierarchicalBox KeystoneCorrection
344. Content of HierarchicalBox DistortionCorrection
345. Content of HierarchicalBox DistortionCoefficient
346. Example Source Image [Ope16a]
347. Distortion and Keystone corrected target image
348. Rotated, distortion and Keystone corrected target image
349. Basic design structure of the VA design "DistortionCorrection.va"
350. Content of HierarchicalBox DistortionCorrection
351. Content of HierarchicalBox InverseCorrection
352. Basic design structure
353. Content of ImageMoments
354. Content of the HierarchicalBox orientation_theta
355. Content of the HierarchicalBox eccentricity
356. Skew of a scanned object resulting from camera misalignment
357. Basic design structure
358. Content of HierarchicalBox LineShear
359. Content of HierarchicalBox ExtractInteger
360. Content of HierarchicalBox Select
361. Content of HierarchicalBox TransformedYCoordinate
362. Shift corrected image
363. Basic design structure for scaling a line camera image
364. Components of Transformation
365. Components of WordToRead
366. Components of PixelPicker
367. Content of Pick_0
368. Components of Interpolation
369. Basic design structure for "TapSorting_2XE_1Y.va"
370. Basic design structure of "TapSorting_2X_2Y.va"
371. Content of the HierarchicalBox Address in "TapSorting_2X_2Y.va"
372. Basic design structure of "TapSorting_8X_1Y.va"
373. Content of the HierarchicalBox Sorting_8X_1Y
374. Content of the HierarchicalBox Address in "TapSorting_8X_1Y.va"
375. Basic design structure
376. Content of box Trigger
377. Content of box HDR
378. Content of component Red in Image1
379. Content of box Red under HDR
380. Content of box LDR in the designs "HDR_CRC_Bayer.va" and "HDR_CRC_Color.va"
381. Content of box LDR in the design "HDR_CRC_Gray.va"
382. Basic design structure
383. Content of box HDR
384. Content of Red in box Image1
385. Content of Red in box HDR
386. Basic design structure of "ExposureFusion.va"
387. Content of HierarchicalBox ExposureFusion
388. Content of HierarchicalBox ImageComposition
389. Content of HierarchicalBox Weight
390. Content of HierarchicalBox Red in box Weight
391. Content of HierarchicalBox Red in box ImageComposition
392. Example input images with different exposure times
393. Result image of the 5 example input images after exposure fusion
394. Basic design structure
395. Content of HierarchicalBox DepthFromFocus
396. Content of HierarchicalBox CompareContrast
397. Content of HierarchicalBox SelectDepthIndex
398. Content of HierarchicalBox SelectPixelValue
399. Content of HierarchicalBox LastImageOfSequenceOnly
400. Basic Design structure of the VA designs "HOG_9Bins_Histogram.va","HOG_9Bins_HistogramMax.va" and "HOG_4Bins_HistogramMax.va"
401. Content of HierarchicalBiox HOG
402. Content of HierarchicalBox GradientFilter
403. Content of HierarchicalBox MagnitudeOrientation
404. Content of HierarchicalBox Histogram
405. Content of HierarchicalBox Bin1
406. Content of HierarchicalBox ConcatenateWithNeighbors
407. Content of HierarchicalBox GetHistogramMax
408. Basic design structure of the VA design "PrintInspection_Blob.va"
409. Content of the HierarchicalBox FindPatterns
410. Content of the HierarchicalBox ExtractCandidates
411. Content of the HierarchicalBox DetermingCOGTemplates
412. Content of the HierarchicalBox TemplateMatching
413. Content of the HierarchicalBox COG_Angle
414. Basic design structure of the VA design "PrintInspection_ImageMoments.va"
415. Basic design structure of "NormalizedCrossCorrelation.va"
416. Test image "PCB.tif"
417. Content of HierarchicalBox NCC
418. Content of HierarchicalBox Division
419. result image with "1" at object positions (zoomed view)
420. Hierarchical Box ImageTrigger of the TrgPortLine Rebuild Example
421. Hierarchical Box LineTrigger of the TrgPortLine Rebuild Example
422. Objects Visualized by Colored Boxes
423. 4-Connected Neighborhood
424. 8-Connected Neighborhood
425. Pixels allocated to objects in a 4-connected neighborhood (left) and an 8-connected neighborhood (right). All colored pixels represent foreground pixels where their allocation to objects is visualized by differing colors.
426. 4-connected neighborhood: Contour Orthogonal = 30, Diagonal = 0
427. 8-connected neighborhood: Contour Orthogonal = 14, Diagonal = 8
428. Calculation of the perimeter using an 8-connected neighborhood (left) and a 4-connected neighborhood (right)
429. Blob Analysis Operators
430. Behavior of the Blob Analysis 1D Operator
431. Synchronization of the Blob 1D Operator in a VisualApplets Network
432. Blob 1D Timing - Generation of New Frames
433. Blob 1D Timing - Suppression of Empty Frames
434. Blob 1D Timing - Constant Flush
435. Blob 1D Timing - Discarding of Objects
436. Simulation Scenario 1 - Flush and Y0 Relation
437. Simulation Scenario 2 - Flush Pixel Position
438. Simulation Scenario 3 - Discarded Flush Pixel at End of Frame
439. Simulation Scenario 4 - Multiple Blobs
440. Formula for calculating the minimum input image width
441. Overflow Event Data
442. This configuration is equivalent to a simpler CxpCamera operator with only O output and no meta data.
443. This configuration is equivalent to a simpler CxpCamera operator with port O and MetaDataO selected.
444. In this configuration only the tap 0 is output with its metadata. For the tap 1 only the metadata is output. This configuration can be useful for debugging a camera/frame grabber combination.
445. In this configuration the operator provides both camera taps as 2 separate data streams on its Tap0 and Tap1 ports. However, no metadata information is output.
446. In this configuration the operator provides both camera taps as 2 separate streams on its Tap0 and Tap1 ports. The operator provides also the meta information for the Tap0 port. This configuration might be meaningful for symmetrical camera tap configurations, where the CXP header is in most parts identical for both taps except for the TapG Code fields.
447. This is the maximal configuration of the operator, where for each tap an own output is presented together with its own metadata.
448. RAM architecture

List of Tables

1. Operator Types
2. Availability of Autocompletion and Syntax Highlighting
3. List of Device Resources
4. Operator/Info
5. Operator/IO
6. Operator/Properties
7. Operator/ImgIn
8. Operator/ImgOut
9. Operator/RegIn
10. Operator/RegOut
11. Operator/Mem
12. Operator/Core
13. Commands for Creating and Editing a VA Design in Tcl
14. Command Line Options and According Arguments
15. Shortcut List for Main Program Window
16. Shortcut List for Simulation Viewer
17. List of Basic Acquisition Examples
18. Design Versions for Grayscale JPEG Encoding
19. Design Versions for Color JPEG Encoding
20. List of Bayer Demosaicing Examples
21. Overview of Color Separation Examples
22. List of Geometric Transformation Examples
23. Reading Cycles
24. Files and their corresponding lookup tables in Visual Applets
25. Examples of tap geometries
26. Available Libraries
27. Operators of Library Accumulator
28. Operators of Library Arithmetics
29. Operators of Library Base
30. Examples
31. Explanation of pseudo-code
32. Examples
33. Examples
34. Operators of Library Blob
35. Explanation of Blob Error Flags
36. Explanation of Blob Error Flags
37. Operators of Library Color
38. Operators of Library Compression
39. Operators of Library Debugging
40. Operators of Library Filter
41. Operators of Library Logic
42. Memory Types of Operators in the Library Memory
43. Individual Latencies of the Operators in Library Memory
44. Operators of Library Memory
45. Data types supported by reference operators
46. Operators of Library Parameters
47. Basic operations
48. Functions
49. Basic operations
50. Functions
51. Basic operations
52. Functions
53. Operators of Library Hardware Platform
54. Mapping VA notation and CL Specification Version 2.1
55. Mapping VA notation and CL Specification Version 2.1
56. Mapping VA notation and CL Specification Version 2.1
57.
58.
59.
60.
61. Operators of Library Prototype
62. Operators of Library Signal
63. Operators of Library Synchronization
64. Operators of Library Transformation
65. Hardware Configuration microEnable IV and PixelPlant
66. Hardware Configuration microEnable 5 ironman
67. Hardware Configuration LightBridge and microEnable 5 marathon
68. Hardware Configuration imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
69. List of Device Resources microEnable IV and PixelPlant
70. List of Device Resources microEnable 5 ironman
71. List of Device Resources LightBridge and microEnable 5 marathon
72. List of Device Resources imaFlex CXP-12 Quad and imaFlex CXP-12 Penta

List of Equations

1. Overlay Blend
2. Optimized Overlay Blend for FPGA Implementation

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